High-speed CML push-pull logic circuit having temperature compen

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307446, 307310, H03K 19003

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active

052372162

ABSTRACT:
A negative-phase output signal in an ECL circuit is extracted by an emitter-follower circuit, and the extracted signal is differentiated at its leading edge by a capacitor driven by the emitter-follower circuit so as to form a pulse wave, thus the differentiated signal drives a transistor connected in parallel with an emitter-follower resistor to which a positive-phase output signal is supplied. With this operation, a large amount of current flows only at the trailing edge of the output signal to shorten the fall time of the output from the logic circuit.

REFERENCES:
patent: 4680480 (1987-07-01), Hopta
patent: 4835420 (1989-05-01), Rosky
patent: 4855622 (1989-08-01), Johnson
patent: 4874970 (1989-10-01), Coy et al.
patent: 5047670 (1991-09-01), Tran
patent: 5066876 (1991-11-01), Fukuda et al.
patent: 5101124 (1992-03-01), Estrada
patent: 5124581 (1992-06-01), Umeki
Chuang et al, A 23-ps/2.1-mW ECL Gate With An AC-Coupled Active Pull-Down Emitter-Follower Stage, IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1301-1306.

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