Asynchronous interrupt status bit circuit

Details Asynchronous interrupt status bit circuit Asynchronous interrupt status bit circuit

1988-06-13

1989-08-29

Shaw, Gareth D.

Boots, shoes, and leggings

3649278, 364941, 3649418, 3649417, G06F 900

Patent

active

048624098

ABSTRACT:
An asynchronous interrupt status bit circuit for use in conjunction with a microprocessor, which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice, includes a master latch (12), a transfer gate (14), a clocked latch (16), an inverter (18), an output driver circuit (20), and a clearing circuit (22, 24). The master latch (12) is responsive to an interrupt input signal for generating an interrupting logic signal at its output which is latched to a low logic level. The clearing circuit (22, 24) is responsive to a control signal for generating a clear signal to clear the output of the master latch (12) to a high level only when the control signal is latched at a high level before the time a true read signal is making a high-to-low transition. The next read signal causes an output signal having a low level to be read by the microprocessor if no interrupt input signal has occurred.

REFERENCES:
patent: 4716523 (1987-12-01), Burrus, Jr. et al.

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