Trench isolation for CMOS devices

Details Trench isolation for CMOS devices Trench isolation for CMOS devices

1997-08-22

1999-04-20

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438427, 438675, 438701, 438431, 257374, H01L 21306

Patent

active

058952535

ABSTRACT:
The present invention is an isolation trench with an insulator, and a method of forming the same using self-aligned processing techniques. The method is implemented with a single mask. A shallow trench is first formed with the mask. Subsequently, the deep trench is formed in self-alignment to the shallow trench. The shallow and deep trenches are filled with insulators. The deep trench diminishes the effects of undesirable inter-device affects, such as leakage current and latch-up. As a result, substrates can be fabricated with high device density.

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