Method of manufacturing a semiconductor device with vertically s

Details Method of manufacturing a semiconductor device with vertically s Method of manufacturing a semiconductor device with vertically s

1991-11-25

1993-08-17

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 72, 437 73, H01L 21265, H01L 2170

Patent

active

052368580

ABSTRACT:
The invention relates to a method of manufacturing a DRAM in which a storage capacitor is stacked vertically over a switching junction FET. There is provided a method comprising the steps of: (a) sequentially depositing a nitride layer and a first oxide layer on a substrate; (b) etching away the oxide and nitride layer by means of a trench mask so as to define field and active regions; (c) etching away the substrate of the field region up to a predetermined depth using the remaining oxide and nitride layers as a mask so as to form trench portion; (d) forming a first spacer at the edges of the trench portion; (e) further etching away the substrate of the field region up to a predetermined depth using the remaining oxide and nitride layers and the first spacer as a mask; (f) forming a second spacer at edges of the trench portion; (g) growing a device isolating field oxide layer of the field region after etching away the substrate of the field region; (h) depositing a polysilicon layer thereon after removal of the second spacer and implanting impurity into the substrate through the polysilicon layer so as to form a gate junction region; (i) etching away the polysilicon layer only on the field region so as to define a word line; (j) growing an insulating layer in the field region and removing the first oxide layer on the nitride layer; (k) flatting projected portions of the polysilicon layer and forming an oxide layer on the projected portion and the insulating layer so as to self-contact between storage node of the storage capacitor and drain of the junction FET; (I) depositing a patterned polysilicon layer for the storage node thereon and forming a capacitor dielectric layer around the patterned polysilicon layer; and (m) depositing a polysilicon layer for a plate electrode and defining a bit line by means of a bit line mask.

REFERENCES:
patent: 4434433 (1984-02-01), Nishizawa
patent: 4891327 (1990-01-01), Okumura
patent: 4920065 (1990-04-01), Chin et al.
patent: 5013679 (1991-05-01), Kumagai et al.
patent: 5082795 (1992-01-01), Temple

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