Semiconductor wafer with an electrically-isolated semiconductor

Details Semiconductor wafer with an electrically-isolated semiconductor Semiconductor wafer with an electrically-isolated semiconductor

1985-12-11

1989-08-29

Hille, Rolf

357 22, 357 13, 357 86, 357 52, H01L 2704, H01L 2980, H01L 2990, H01L 2934

Patent

active

048622427

ABSTRACT:
A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device can accordingly be operated at high voltage with respect to the wafer substrate. The isolation structure in one form of the wafer comprises an N+ high voltage tub included in the wafer and a P+ ground region situated in the expitaxial layer, adjoining the substrate, and horizontally circumscribing the N+ high voltage tub and being spaced therefrom by a minimum layer extent of a portion of the epitaxial layer that is of N conductivity type. The N+ high voltage tub comprises an N+ high voltage region situated in the epitaxial layer and surrounding a device region in which the semiconductor device is at least partially contained and, further, an N+ buried layer underlying the N+ high voltage region and the entirety of the device region.

REFERENCES:
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patent: 4277794 (1981-07-01), Nuzillat
patent: 4292642 (1981-09-01), Appels et al.
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patent: 4494134 (1985-01-01), Wildi et al.
patent: 4809021 (1978-05-01), Sato et al.
Appels, High Voltage Thin Layer Devices (RESURF Devices), IEDM Washington, Dec. 1979, pp. 238-241.

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