Transistor structure for high temperature logic circuits with in

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357 49, 357 50, 357 42, 357 233, H01L 2978

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048622320

ABSTRACT:
A high temperature logic field effect transistor. By surrounding the source and drain pn junctions with electrically insulative material, except where a channel runs between the source and drain, a logic field effect transistor whose on/off current ratio can still have a high value at high temperatures. The transistor can be of any standard MOS technology, such as pMOS, nMOS, or CMOS.

REFERENCES:
patent: Re31580 (1984-05-01), Kooi
patent: 3544858 (1970-05-01), Kooi
patent: 3763408 (1973-10-01), Kano et al.
patent: 3806371 (1974-04-01), Barone
patent: 3958040 (1976-05-01), Webb
patent: 3961358 (1976-06-01), Polinsky
patent: 3965481 (1976-06-01), Esser
patent: 4065781 (1977-12-01), Gutknecht
patent: 4091527 (1978-05-01), Goodman et al.
patent: 4101922 (1978-07-01), Tihanyi et al.
patent: 4143388 (1979-03-01), Esaki et al.
patent: 4178197 (1979-12-01), Marinace
patent: 4241359 (1980-12-01), Izumi et al.
patent: 4333965 (1982-06-01), Chow et al.
patent: 4384301 (1983-05-01), Tasch, Jr. et al.
patent: 4487639 (1984-12-01), Lam et al.
patent: 4522682 (1985-06-01), Soclof
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4532700 (1985-08-01), Kinney et al.
patent: 4533431 (1985-08-01), Dargent
patent: 4536782 (1985-08-01), Brown
patent: 4571606 (1986-02-01), Benjamin et al.
patent: 4621276 (1986-11-01), Malhi
Anantha et al, "Integrated Circuits . . . Devices" IBM TDB vol. 16, No. 10, Mar. 74, pp. 3245.
"A Bird's Beak Free Local Oxidation Technology Feasible for VSLI Circuits Fabrication," Kuang Yi Chiu et al, IEEE Transaction on Electron Devices, vol. ED-29, No. 4 Apr. 1982, pp. 536-540.
"Alternatives to LOCOS Could Aid Isolation Technology," Semiconductor International L19, Mar. 1984.
"Selective Low-Pressure Silicon Epitaxy for MOS and Bipolar Transistor Application," Hans Kurter et al, IEEE Transactions on Electron Devices, vol. ED-30, No. 11, Nov. 1983, pp. 1511-1515.
"The Sloped-Wall SWAMI-A Defect-Free Zero Bird's Beak Local Oxidation Process for Scaled VLSI Technology," Kuang Y. Chiu et al., IEEE Transactions on Electron Devices, vol. ED-30, No. 11, Nov. 1983, pp. 1506-1511.
"Development of the Self-Aligned Titanium Silicide Process for VLSI Application," Michael E. Alperin et al., IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 61-65.

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