High speed, low drift sample and hold circuit

Details High speed, low drift sample and hold circuit High speed, low drift sample and hold circuit

1984-12-24

1989-08-29

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

328151, G11C 2702

Patent

active

048620165

ABSTRACT:
A sample and hold circuit which achieves both a fast acquisition time and a low droop rate is disclosed. FET or analog switches form a sample switch. When this circuit is in a hold mode the sample switch is biased so that no voltage appears across the switch. However, only one switch or a plurality of switches in parallel connect between a driving buffer and hold capacitor so that a fast acquisition time is achieved when this circuit is in a sample mode.

REFERENCES:
patent: 3390347 (1968-06-01), Jones et al.
patent: 3516002 (1970-06-01), Hillis
patent: 3686577 (1972-08-01), Fruhauf
patent: 3696305 (1972-10-01), Mitchell et al.
patent: 4209717 (1980-06-01), Mahony
patent: 4302689 (1981-11-01), Brodie
Signetics Analog, Applications Manual, Jan. 1979, pp. 42-45 & 322-325.
National Linear Applications, vol. I, 1976, pp. An4-3, AN4-4, AN5-8, AN5-10, AN29-6, AN29-7, AN32-1, AN32-6, AN32-7, AN63-7, AN63-8, AN75-3.

Affiliated with

Also associated with

Rating

High speed, low drift sample and hold circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed, low drift sample and hold circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed, low drift sample and hold circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2240505