Reconfigurable decoding scheme for memory address signals that u

Details Reconfigurable decoding scheme for memory address signals that u Reconfigurable decoding scheme for memory address signals that u

1974-06-27

1976-05-18

Nusbaum, Mark E.

Communications: electrical

Digital comparator systems

G06F 910

Patent

active

039582221

ABSTRACT:
This specification describes an associative memory decoder for a memory system in which the units in the memory system are reconfigurable both in size and in number. The decoder is designed to take an address for that memory system and address memory space in the memory system irrespective of the amount of storage in the system so that the decoder has to change as memory capacity is added or subtracted from the memory system.

REFERENCES:
patent: 3533075 (1970-10-01), Johnson et al.
patent: 3585605 (1971-06-01), Gardner et al.
patent: 3676857 (1972-07-01), Jackson
patent: 3691531 (1972-09-01), Saltini et al.
patent: 3764996 (1973-10-01), Ross
patent: 3840863 (1974-10-01), Fuqua et al.

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