Synchronous memory device of a wave pipeline structure

Details Synchronous memory device of a wave pipeline structure Synchronous memory device of a wave pipeline structure

1999-05-26

2000-12-12

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800

Patent

active

061607541

ABSTRACT:
A synchronous memory device of a wave pipeline structure includes: an internal clock signal generation means which generates an internal clock signal being a standard of an output data only during a period in which an output enable signal is activated; and a data transmission means which is connected between an output terminal of a plurality of registers and an output driver, is switched by a control of the internal clock signal, receives data stored in an activated register as input, and transmits the data to the output driver. As a result, the synchronous memory device greatly improves the data access path and the data output hold time, enhances the stability and performance of a memory operation, and achieves a high-speed operation.

REFERENCES:
patent: 4931993 (1990-06-01), Urushima
patent: 5369618 (1994-11-01), Takasugi
patent: 5568427 (1996-10-01), Takemae
patent: 5838631 (1998-11-01), Mick

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