Semiconductor memory device allowing efficient column selection

Details Semiconductor memory device allowing efficient column selection Semiconductor memory device allowing efficient column selection

1999-07-12

2000-12-12

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

061607517

ABSTRACT:
In a memory mat of a semiconductor memory device according to the present invention, a main column select line is provided for every n column addresses and a n sub column select lines are arranged for every main column select line (n is a natural number). In response to a column address signal, a main column select line is selected and a burst circuit and a sub decoder activate a corresponding sub decode signal. A sub column decoder drives a sub column select line according to the states of the main column select line and the sub decode signal.

REFERENCES:
patent: 5487050 (1996-01-01), Kim et al.
patent: 5715209 (1998-02-01), Yoo
patent: 5822268 (1998-10-01), Kirihata
"A 32-Bank 1 Gb Self-Strobing Synchronous DRAM with 1 Gbyte/s Bandwidth" by Yoo, et al., IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996.

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