Minimizing hardware pipeline breaks using software scheduling te

Details Minimizing hardware pipeline breaks using software scheduling te Minimizing hardware pipeline breaks using software scheduling te

1989-12-21

1992-06-02

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG1, 3642318, 3642631, 364263, 3642476, 3642592, G06F 906

Patent

active

051194953

ABSTRACT:
A compiler module is disclosed which minimizes pipeline breaks by reordering object code instructions to avoid conflicts between closely grouped instructions to the extent possible. Representation of each object code instruction in a small sequential group is temporarily held in a buffer and is assigned a pair of Attribute Words. Potential conflicts which a newly called instruction may have with those instructions already in the buffer are ascertained by logically AND-ing its Attribute Word with those of the other instructions and examining the result. If a conflict does exist, an attempt is made to resolve it by determining if the conflicting instruction already in the buffer can be moved ahead of one or more other instructions in the buffer such that the conflict is eliminated or minimized. This procedure involves a comparison of the Attribute Words of the candidate instruction to be moved, I.sub.m, with the other instructions in the buffer. If movement of the conflicting instruction is possible and will resolve or minimize the conflict, the instructions in the buffer are reordered as appropriate.

REFERENCES:
patent: 4295193 (1981-10-01), Pomerene
patent: 4493027 (1985-01-01), Katz et al.
patent: 4965724 (1990-10-01), Utsumi et al.

Affiliated with

Also associated with

Rating

Minimizing hardware pipeline breaks using software scheduling te does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimizing hardware pipeline breaks using software scheduling te, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimizing hardware pipeline breaks using software scheduling te will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2236603