Method of manufacturing flat panel backplanes, display transisto

Details Method of manufacturing flat panel backplanes, display transisto Method of manufacturing flat panel backplanes, display transisto

1983-05-11

1988-04-05

James, Andrew J.

357 237, 357 54, 357 71, 357 30, H01L 2712

Patent

active

047362294

ABSTRACT:
An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.

REFERENCES:
patent: 3675090 (1972-07-01), Neale
IBM Technical Disclosure Bulletin, vol. 21, #4, pp. 1666-1667, Sep. 1978 by Chapman.
1982, SID Intl. Symposium Digest of Technical Papers, pp. 40-41 by Okubo et al., May 1982.
Snell et al., "Application of Amorphous Silicon Field Effect Transistors in Addressable LCD Panels," Appl. Phys. 24, 357-362 (1981).

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