Method to provide a reduced constant E-field during erase of EEP

Details Method to provide a reduced constant E-field during erase of EEP Method to provide a reduced constant E-field during erase of EEP

2000-01-24

2000-12-12

Elms, Richard

Static information storage and retrieval

Floating gate

Particular biasing

36518533, 36518518, 36518524, G11C 1604

Patent

active

061607401

ABSTRACT:
A method to reduce the peak electric field during erase of a memory device composed of multiple memory cells. The electric field E.sub.field of the memory cell during erase is determined by the equation E.sub.field .about.a.sub.g (V.sub.gate -V.sub.th +V.sub.tuv)+(a.sub.s -1)V.sub.source and varying gate voltages V.sub.gate are applied to the gate of the cell being erased so that the V.sub.gate -V.sub.th is constant during the erase procedure.

REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5428578 (1995-06-01), Kaya et al.
patent: 5680348 (1997-10-01), Chung et al.
patent: 5805502 (1998-09-01), Tang et al.
patent: 5917757 (1999-06-01), Lee et al.
patent: 6049479 (2000-04-01), Thurgate et al.

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