Data processing system having redundant control processors for f

Details Data processing system having redundant control processors for f Data processing system having redundant control processors for f

1980-11-06

1984-06-26

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

044569521

ABSTRACT:
A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store. The system includes an input circuit for simultaneously supplying to the first and second control processors a micro-instruction which the control store reads out upon receipt of said micro-address from the micro-address comparator, and a CPU-to-cache interface comparator including a second comparator circuit for comparing memory-addresses given from the first and second control processors, and then combines these memory-addresses to form one memory address and supplies the memory-address to the cache memory. The first and second control processors are simultaneously supplied with an operand which the cache memory reads out upon receipt of the memory-address from the CPU-to-cache interface comparator. The system is further provided with a fault processing circuit for supplying a clock stop signal to the first and second control processors when at least one of the first and second comparator circuits produces a non-coincidence signal, whereby the first and second control processors execute the microinstructions from the control store to carry out arithmetic operations, using the operand when necessary and stops executing the microinstructions upon receipt of the clock stop signal from the fault processing circuit.

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