1981-10-06
1984-06-26
James, Andrew J.
357 41, 357 43, 357 89, 357 48, H01L 2980, H01L 2702, H01L 2704
Patent
active
044569181
ABSTRACT:
A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.
REFERENCES:
patent: 3223904 (1965-12-01), Warner, Jr. et al.
patent: 3649385 (1972-03-01), Kobayashi
patent: 4143392 (1979-03-01), Mylroie
patent: 4176368 (1979-11-01), Compton
patent: 4187514 (1980-02-01), Tomisawa et al.
patent: 4322738 (1982-03-01), Bell et al.
"JFET-Transistor Yields Device with Negative Resistance", John A. Porter, IEEE Transactions on Electron Devices, Sep. 1976, pp. 1098-1099.
Harris Corporation
James Andrew J.
Lamont John
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