Power line disturbance detector circuit

Details Power line disturbance detector circuit Power line disturbance detector circuit

1979-02-26

1981-01-13

Thesz, Joseph M.

Registers

Platform operated

Platform actuated traffic counters

235 92PE, 340663, 361 92, 364900, G06M 312, H02H 324

Patent

active

042451507

ABSTRACT:
A power line disturbance (PLD) detector circuit includes a digital counter which is driven by pulses provided by a clock in an associated data processing system. The PLD detector circuit includes a comparator amplifier for comparing primary AC power to a DC reference voltage on a cycle-by-cycle basis. The amplifier generates a reset pulse once during each AC cycle as long as the AC voltage exceeds the DC reference voltage. When a decoder circuit detects a count outside the range of counts attained by the digital counter between normally occurring reset pulses, the decoder circuit responds by generating a PLD signal. The PLD signal is provided both to the associated data processing system and to a Power On Reset circuit. The Power On Reset circuit is initialized by the PLD signal, permitting the circuit to respond consistently upon subsequent restoration of power.

REFERENCES:
patent: 3852731 (1974-12-01), Hollands
patent: 3885199 (1975-05-01), Nohara et al.
patent: 3937937 (1976-02-01), McVey
patent: 3944889 (1976-03-01), Conway
patent: 4031463 (1977-06-01), Norberg
patent: 4089058 (1978-05-01), Murdock

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