Method for forming a narrow channel length MOS field effect tran

Details Method for forming a narrow channel length MOS field effect tran Method for forming a narrow channel length MOS field effect tran

1976-08-05

1978-03-14

Ozaki, G.

Metal treatment

Compositions

Heat treating

148187, 357 43, 357 91, H01L 2126

Patent

active

040789470

ABSTRACT:
A method for fabricating an N-channel silicon MOS field effect transistor on a P-type substrate. The structure retains the natural isolation between devices and the consequent higher device density in an integrated circuit structure than conventional double diffused MOS field effect transistor devices. The device is fabricated by using ion implantation to create an N-type surface layer in the channel and then overcompensating this layer to create a P-type region near the source by ion implanting P-type ions into the source junction region. The source to substrate capacitance is considerably less than that of conventional double diffused MOS devices which provides an improved circuit performance.

REFERENCES:
patent: 3873372 (1975-03-01), Johnson
patent: 3876472 (1975-04-01), Polinsky
patent: 3883372 (1975-05-01), Lin
patent: 3895390 (1975-07-01), Meiling et al.
patent: 3909320 (1975-09-01), Gauge et al.
patent: 3926694 (1975-12-01), Cauge et al.
patent: 3933529 (1976-01-01), Goser
patent: 3967981 (1976-07-01), Yamazaki

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