Process for fabricating a semiconductor device having an improve

Details Process for fabricating a semiconductor device having an improve Process for fabricating a semiconductor device having an improve

1995-05-23

1996-06-18

Fourson, George

Fishing, trapping, and vermin destroying

437192, 437194, 437246, H01L 2128

Patent

active

055277390

ABSTRACT:
A metal interconnect structure includes copper interface layers (24, 30) located between a refractory metal via plug (28), and first and second metal interconnect layers (16, 32). The copper interface layers (24, 30) are confined to the area of a via opening (22) in an insulating layer (20) overlying the first interconnect layer (16) and containing the via plug (28). The interface layers (24, 30) are subjected to an anneal to provide copper reservoirs (36, 37) in the interconnect layers (16, 32) adjacent to the interface layers (24, 30). The copper reservoirs (36, 37) continuously replenish copper depleted from the interface when an electric current is passed through the interconnect structure. A process includes the selective deposition of copper onto an exposed region (23) of the first metal interconnect layer (16), and onto the upper portion the via plug (28), followed by an anneal in forming gas to form the copper reservoirs (36, 37).

REFERENCES:
patent: 3743894 (1973-07-01), Hall et al.
patent: 4335506 (1982-06-01), Chiu et al.
patent: 4812419 (1989-03-01), Lee et al.
patent: 5187300 (1993-02-01), Norman
patent: 5202579 (1993-04-01), Fujii et al.
patent: 5284799 (1994-02-01), Sato
Tao, et al., Proc. 1991 VLSI Multilevel Interconnect Conf., pp. 390-392, "Electromigration Characteristics of Al/W via Contact Under Unidirectios".
Hu et al., 1991 MRS Symposium Proceedings, 225, pp. 99-105, "Electromigration in Al/W and Al(W)/w Interconnect Structures".
Filippi, et al., 1992 VLSI multilevel Interconnect Conf., pp. 359-365.
Tao, et al., 1992 IRPS Proceedings, pp. 338-343.
d'Heurle et al., "Metallization For Shallow Junction Silicon Technology, IBM Technical Disclosure Bulletin", vol. 19, No. 8, Jan. 1977, pp. 3232-3233.

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