Selective formation of low-density, low-dielectric-constant insu

Details Selective formation of low-density, low-dielectric-constant insu Selective formation of low-density, low-dielectric-constant insu

1994-05-27

1996-06-18

Fourson, George

Fishing, trapping, and vermin destroying

437235, H01L 2144

Patent

active

055277373

ABSTRACT:
An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on. One advantage of the invention is providing a metallization scheme that reduces line-to-line capacitance. A further advantage of the invention is providing a metallization scheme that reduces crosstalk and power dissipation. A further advantage of the invention is providing a dielectric layer between interconnect lines having a lower density and a lower dielectric constant than dense silicon dioxide.

REFERENCES:
patent: 5043789 (1991-08-01), Linde et al.
patent: 5119170 (1992-06-01), Iwamatsu
patent: 5223804 (1993-06-01), Usui
patent: 5250472 (1993-11-01), Chen et al.
patent: 5371046 (1994-12-01), Liaw et al.

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