Method of manufacturing a self-aligned U-MOS semiconductor devic

Details Method of manufacturing a self-aligned U-MOS semiconductor devic Method of manufacturing a self-aligned U-MOS semiconductor devic

1982-09-29

1984-06-26

Massie, Jerome W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 29591, 156648, 156649, 156653, 156657, 357 55, 357 23, H01L 21308, H01L 21283, H01L 2122

Patent

active

044557400

ABSTRACT:
A method of manufacturing a MOS semiconductor device, which comprises a step of forming a groove in a predetermined portion of a semiconductor substrate, a step of forming a gate insulation film to cover the entire surface of the substrate inclusive of the groove, a step of depositing a gate electrode material to a thickness greater than one half the width of the opening of the groove to thereby fill the groove with the gate electrode material, and a step of forming a gate electrode within the groove by etching away the gate electrode material until the gate insulation film other than that within the groove is exposed. Before the step of etching the gate electrode material, a portion of the gate material layer including a portion thereof over part of the groove and/or a portion of the layer other than that within the groove may be covered with a mask material to simultaneously form a lead integral with the gate electrode within the groove and/or a separate gate electrode at the time of the etching of the gate electrode material.

REFERENCES:
patent: 4219835 (1980-08-01), van Loon et al.
patent: 4225879 (1980-09-01), Vinson
patent: 4238278 (1980-12-01), Antipov
patent: 4326332 (1982-04-01), Kenney
Nishimatsu et al., "Grooved Gate MOSFET," Jap. J. of Applied Physics, vol. 16 (1977), pp. 179-183.
Holmes, "A VMOS-. . . Circuits," IEEE Transactions Electron Devices, vol. 24, No. 6, (6/77), pp. 771-774.

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