Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1992-09-22

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

36523004, 36523008, G11C 700

Patent

active

053233557

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a semiconductor memory device such as a dynamic RAM and, more particularly to a dynamic RAM capable of reading different data sequentially by changing an initial address in the same read cycle and of increasing a reading speed in a nibble mode.


TECHNICAL BACKGROUND

Dynamic RAMs (hereinafter referred to as DRAMs) have been recently required to be usable in a flexible manner in a variety of modes. There are nibble mode type of DRAMs that are available which are designed to simultaneously read data consisting of a plurality of bits of data to a plurality of pairs of bus lines, and to output the data read out to the respective pairs of bus lines one by one in order to increase a data reading speed. There are proposed a variety of extended nibble modes in the nibble mode type of DRAMs.
A DRAM of the conventional nibble mode type is shown in FIG. 14. A memory cell array 11 includes a plurality of memory cells. To the array 11 are connected a row decoder 12, a sense amplifier and input/output (I/O) gate 13, and a column decoder 14. To the sense amplifier and I/O gate 13 is connected a gate circuit 15, to which is connected a data output buffer 16.
To the row decoder 12 is connected a row address buffer 17, which feeds to a row decoder 12 an external address signal AD including a plurality of bits input from an unillustrated controller unit.
A row controller 18 controls the row decoder 12 and the row address buffer 17 based on the levels of a row address strobe signal RAS and a column address strobe signal CAS, both serving as address activating signals.
To the column decoder 14 is connected a column address buffer 19, which feeds to the column decoder 14 an external address signal AD including a plurality of bits input from the controller.
A column controller 20 controls the sense amplifier and I/O gate 13, the column decoder 14, and the column address buffer 19 based on the level of an output signal of an AND circuit 21 to which a control signal RASZ from the row controller 18 and the column address strobe signal CAS are input.
A clock generating circuit 22 including an odd number of inverter circuits receives the column address strobe signal CAS, and outputs to a nibble counter 23 a clock signal CLK having a negative phase to the signal CAS as shown in FIG. 17. The nibble counter 23 counts the clock signal CLK input from the clock generating circuit 22, and outputs its counted result to a nibble decoder 24. The nibble decoder 24 decodes a counted value of the nibble counter 23, and outputs to a gate control circuit 25 control signals .phi. A to .phi. D shown in FIG. 17.
The gate control circuit 25 takes an AND (logical product) of the control signals .phi. A to .phi. D from the nibble decoder 24 and the clock signal CLK from the clock generating circuit 22, and outputs control signals .phi. 11 to .phi. 14 shown in FIG. 17 to the gate circuit 15 so as to control the gate circuit 15.
A data input buffer 26 is connected to the sense amplifier and I/O gate 13, and receives a write data Din based on a control signal from an unillustrated write clock generator.
FIGS. 15 and 16 show in detail the memory cell array 11, the sense amplifier and I/O gate 13, the gate circuit 15, and the data output buffer 16. As shown in FIG. 15, a data bus 30 includes four pairs of data bus lines DB0, DB0 to DB3, DB3, to which pairs of bit lines BL0, BL0 to BL3, BL3 are connected, respectively. The pairs of bit lines BL0, BL0 to BL3, BL3 are connected to memory cells 32 each having one end thereof connected to a word line WL through gate transistors T1 and a sense amplifier 31.
On the respective pairs of data bus lines DB0, DB0 to DB3, DB3 are arranged amplifiers 33. Gate circuits 15 each including nMOS transistors T2, T3 are provided at the output sides of each amplifier 33 as shown in FIG. 16. The control signal .phi. 11 is input to gates of the nMOS transistors T2, T3 arranged on the pair of bus lines DB0, DB0. The control signal .phi. 12 is input to gates of the nMOS transistors T2

REFERENCES:
patent: 4807192 (1989-02-01), Nakano et al.
patent: 4876671 (1989-06-01), Norwood et al.
patent: 4899312 (1990-02-01), Sato
patent: 5105389 (1992-04-01), Matsuo et al.

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