Method of manufacturing split gate EEPROM cells

Details Method of manufacturing split gate EEPROM cells Method of manufacturing split gate EEPROM cells

1995-09-26

1996-06-18

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 26, 437984, H01L 218247

Patent

active

055277276

ABSTRACT:
The present invention discloses a method of manufacturing flash EEPROM cells. An active region is defined to include a source bit line region and a drain bit line region. When a first polysilicon layer is etched through a floating gate mask work and an etching process, a silicon substrate in the source bit line region and the drain bit line region become exposed. A buried N.sup.+ layer is formed in the exposed silicon substrate by implanting impurity ions. A thick oxide film is formed on the buried N.sup.+ layer by a subsequent oxidation process, and this thick oxide film is etched to a constant thickness by a self-aligned etching process for forming a float gate. Thereafter, a select gate oxide film and a select gate are formed by a general process. The present invention can thus improve the electrical characteristics of a cell by decreasing the topology generated by the oxide film formed in a bit line containing a source region and a drain region, and can simplify the process by forming a bit line containing a source region and a drain region by performing the buried N.sup.+ impurity ion implantation process only once.

REFERENCES:
patent: 4795719 (1989-01-01), Eitan
patent: 4852062 (1989-07-01), Baker et al.
patent: 4924437 (1990-03-01), Paterson et al.
patent: 5162247 (1992-11-01), Hazani
patent: 5395779 (1995-03-01), Hong

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