Low power CMOS frequency divider

Details Low power CMOS frequency divider Low power CMOS frequency divider

1981-01-12

1983-07-26

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Particular output circuits for counter

307452, 307481, 307576, 377121, H03K 2308, H03K 19096

Patent

active

043957749

ABSTRACT:
Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction. The clock input capacitance of the shift register becomes part of the oscillator turning capacitance and thus requires no power dissipation. Furthermore, since the inverters switch at a submultiple of the oscillator frequency, output capacitance charging and discharging power is made negligible.

REFERENCES:
patent: 3749937 (1973-07-01), Rogers
patent: 3922568 (1975-11-01), Hama
patent: 3939642 (1976-02-01), Morozumi
patent: 3958187 (1976-05-01), Suzuki et al.
patent: 3973139 (1976-08-01), Dingwall
patent: 4101790 (1978-07-01), Ebihara et al.

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