Processor implemented communications interface having external c

Details Processor implemented communications interface having external c Processor implemented communications interface having external c

1981-02-17

1983-07-26

Chan, Eddie P.

Boots, shoes, and leggings

G06F 304, G06F 1516

Patent

active

043957560

ABSTRACT:
An automated mailing system includes a postage value determining system processor, a scale for providing weight indicative signals, a keyboard for operator entry of information relating to a determination of postage, and a plurality of peripheral devices. A peripheral controller interface establishes communications links with the peripheral devices. An incompatible systems interface interconnects a serial communications bus of the system processor and the peripheral controller interface. The incompatible systems interface includes a processor programmed to receive, decode and transmit information from or to the system processor along the serial bus and load or receive information from or to the peripheral controller interface along parallel lines. The communication timing constraints of the serial communications bus for receipt of data signals by the system processor do not permit monitoring of the data transmission by the incompatible systems processor. To accommodate for such timing constraints, system clock pulses of the serial bus are employed at a flip-flop to disable the incompatible systems processor.

REFERENCES:
patent: 3909799 (1975-09-01), Recks et al.
patent: 3950735 (1976-04-01), Patel
patent: 4103328 (1978-07-01), Dalmasso
patent: 4246637 (1981-01-01), Brown et al.

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