MOSFET Logic inverter buffer circuit for integrated circuits

Details MOSFET Logic inverter buffer circuit for integrated circuits MOSFET Logic inverter buffer circuit for integrated circuits

1980-12-05

1983-07-26

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307581, 307270, 307279, H03K 19094, H03K 1920, H03K 17687, H03K 3353

Patent

active

043956459

ABSTRACT:
The inverter buffer circuit disclosed includes two transistorized circuits each coupled to an input circuit and an output circuit capable of carrying high current and providing full output swing between a high voltage or binary "1" and a low voltage or binary "0". Each of the two circuits include a first enhancement field effect transistor having its drain electrode connected to a drain voltage and operating as a source follower, a first depletion field effect transistor having its drain electrode and source electrode connected to back bias acting as a load for the first enhancement transistor, second and third enhancement field effect transistors having their source electrodes coupled to the back bias and interconnected to form a flip-flop controlled by the first enhancement transistor and a second depletion field effect transistor having its drain electrode coupled to the drain voltage and acting as the load for the flip-flop. The output circuit includes two depletion field effect transistors connected in series between the drain voltage and source voltage with the gate electrodes thereof connected to a different one of the two flip-flops and an output terminal coupled to the series connection between the two depletion transistors. Three embodiments of the input circuit are disclosed.

REFERENCES:
patent: 3983420 (1976-09-01), Kikuchi
patent: 3995172 (1976-11-01), Freeman et al.
patent: 4004170 (1977-01-01), Henke
patent: 4042839 (1977-08-01), Araki
patent: 4103189 (1978-07-01), Perlegos et al.
patent: 4264829 (1981-04-01), Misaizu
patent: 4280065 (1981-07-01), Minato et al.

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