Method of erasing floating gate capacitor used in voltage regula

Details Method of erasing floating gate capacitor used in voltage regula Method of erasing floating gate capacitor used in voltage regula

1999-01-26

2000-06-06

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518523, G11C 1604

Patent

active

06072725&

ABSTRACT:
A method and an apparatus are provided for the production and supply of an erase voltage for the initial erasing operation of a floating gate transistor used as a capacitor in a voltage regulator, along with the proper electrical connection of the capacitor's control gate and commonly connected regions. In one embodiment, a capacitor erase control circuit controls a pass transistor for connecting the control gate of the floating gate capacitor to ground and another pass transistor for isolating the commonly connected source, drain and channel regions of the floating gate capacitor (the "well node") from ground. The erase control circuit simultaneously applies a capacitor erase input and a clock input to an erase voltage pass circuit to control a third pass transistor to apply an erase voltage to the well node, thereby erasing the floating gate capacitor. The erase control circuit and erase voltage pass circuit are formed on the same semiconductor substrate as the floating gate capacitor and the other components of the voltage regulator. The erasing methodology and apparatus enables economical implementation of an improved voltage regulator using a floating gate transistor.

REFERENCES:
patent: 5406521 (1995-04-01), Hara
patent: 5455790 (1995-10-01), Hart et al.
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5610549 (1997-03-01), Choi

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