Static information storage and retrieval – Floating gate – Particular connection
Patent
1998-07-08
2000-06-06
Nguyen, Tan T.
Static information storage and retrieval
Floating gate
Particular connection
36518518, 36518527, 36518528, 36518529, G11C 1600
Patent
active
060727225
ABSTRACT:
For programming data "0", a reference voltage Vss (e.g., 0 V) is applied to a drain and a source of a memory cell to be programmed via a corresponding main bit line, a corresponding select transistor, and a corresponding local bit line, while a second voltage Vpp (e.g., 15 V) is applied to a control gate of the memory cell via a word line connected with the memory cell. As a result, electrons are injected from the drain, source and channel region to a floating gate of the memory cell via its tunnel oxide. For erasing the memory cell, a third voltage Vds (e.g., 0-6 V) is applied to a semiconductor substrate of the memory cell and a fourth voltage Vneg (e.g., -10 V) is applied to the control gate via the word line. At this time, the third voltage is also applied to the source and drain. Alternatively, the source and drain of the memory cell are placed in a floating state. Consequently, electrons are ejected from the floating gate to the channel region via the tunnel oxide.
REFERENCES:
patent: 5267209 (1993-11-01), Yoshida
patent: 5365484 (1994-11-01), Cleveland et al.
patent: 5402371 (1995-03-01), Ono
patent: 5717636 (1998-02-01), Dallabora
patent: 5777922 (1998-07-01), Choi et al.
patent: 5784325 (1998-07-01), Arase et al.
patent: 5898616 (1999-04-01), Ono
patent: 5920506 (1999-07-01), Wang et al.
"AND" cell structure for a 3 V-only 64Mbit Flash Memory, IEICE, pp:37-43.
Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory, IEEE Journal of Solid-State Circuits, vol. 29, No. 4 (1994), pp:454-9.
An Experimental 4-Mb Flash EEPROM with Sector Erase, IEEE Journal of Solid-State Circuits, vol. 26, No. 4 (1991), pp:484-91.
A Novel Programming Method Using a Reverse Polarity Pulse in Flash EEPROMs, IEICE TRNS. Electron., vol. E79-C, No. 6 (1996), pp:832-5.
Nguyen Tan T.
Sharp Kabushiki Kaisha
LandOfFree
Method of driving a nonvolatile semiconductor storage device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of driving a nonvolatile semiconductor storage device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of driving a nonvolatile semiconductor storage device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2219608