Semiconductor memory device

Static information storage and retrieval – Floating gate – Multiple values

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36518523, 36523006, G11C 1600

Patent

active

060727195

ABSTRACT:
A semiconductor memory device comprises a memory cell array with a plurality of blocks having a plurality of memory cells arranged in a matrix, a plurality of address latch circuits provided so as to correspond to the blocks, a row decoder that accesses the memory cell array in blocks according to the latched state of the plurality of address latch circuits, and a control circuit for accessing the memory cell array by latching all of the blocks to the selected state and then canceling the address latching of the selected block to the unselected state.

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