User selectable word/byte input architecture for flash EEPROM me

Details User selectable word/byte input architecture for flash EEPROM me User selectable word/byte input architecture for flash EEPROM me

1992-06-19

1995-01-03

Canney, Vincent P.

Excavating

371 212, 371 71, G06F 1100

Patent

active

053794133

ABSTRACT:
A circuit for accessing data which may be stored in a flash EEPROM memory array in sixteen bit quantities has apparatus for writing data to the array in eight bit quantities which quantities may be either the lower or upper byte of a word and appear at identical input terminals, apparatus for writing data to the array in sixteen bit quantities, apparatus for reading data from the array to identical output terminals in eight bit quantities which quantities may be either the lower or upper byte of a word, and apparatus for reading data from the array in sixteen bit quantities. The circuit also has apparatus for reading data from the array in eight and sixteen bit quantities during periods in which an erase operation conducted on sixteen bits is suspended.

REFERENCES:
patent: 4672583 (1987-06-01), Nakaizumi
patent: 5132853 (1992-07-01), Kulakowski et al.
patent: 5274648 (1993-12-01), Eikill et al.
Dictionary of Computers, Information Processing & Telecommunications by Jerry M. Rosenberg .RTM.1987 by John Wiley & Sons, Inc., p. 513.
Advanced Microprocessors by Daniel Tabak .RTM.1991 by McGraw-Hill, Inc. pp. 41-59.

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