Multi-trigger logic analyzer

Details Multi-trigger logic analyzer Multi-trigger logic analyzer

1985-04-02

1987-03-31

Harkcom, Gary V.

Excavating

371 15, 371 25, 324 73R, G06F 1100

Patent

active

046548483

ABSTRACT:
Logic data (input data) is sequentially supplied to a data memory using sampling pulses and the input data is written into the data memory at an address specified by an address signal from an address counter which advances by one upon each occurrence of the sampling pulse. The input data and an output trigger word from a trigger word register are compared by a trigger word detector, and when coincidence is detected therebetween, a coincidence signal is generated, which signal is delayed by a delay circuit by a value corresponding to output delay data from a delay register. The delayed output is provided as a stop signal. By the stop signal the address counter is preset to a leading address of a storage area of the data memory into which data is to be stored and the next trigger word is provided from the trigger register. Further, the next delay data is provided from a delay register and the next store number is output from a store-number register. The sampling pulses are counted by a store-number counter, and when the count value coincides with the output store number from the store-number register before the stop signal is generated, the address counter is preset to the leading address of the storage area of the data memory into which data is being written at that time.

REFERENCES:
patent: 4287594 (1981-01-01), Shirasaka
patent: 4313200 (1982-01-01), Nishiura
patent: 4365334 (1982-12-01), Smith et al.
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4434488 (1984-02-01), Palmquist et al.
patent: 4481627 (1984-11-01), Beauchesne et al.
patent: 4497056 (1985-01-01), Sugamori
patent: 4551838 (1985-11-01), Gannett

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