Translation of virtual and real addresses to system addresses

Details Translation of virtual and real addresses to system addresses Translation of virtual and real addresses to system addresses

1983-11-28

1987-03-31

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1210

Patent

active

046547908

ABSTRACT:
An apparatus translates a set of logical addresses to a system addresses where the set of logical addresses includes virtual and real addresses which map to the same system address. An address mechanism provides a requesting field for indicating when a requesting logical address is virtual or when a requesting logical address is real. An address translator translates logical addresses to system addresses. A translation buffer stores translation information for associating logical addresses with system addresses. The translation buffer includes means for storing a resident field for indicating if stored translation information associates a virtual address with a system address, a real address with a system address, or both a real address and a virtual address with a system address.

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