Maximizing improvement to fault coverage of system logic of an i

Details Maximizing improvement to fault coverage of system logic of an i Maximizing improvement to fault coverage of system logic of an i

Filed on

1991-06-19

Date issued

1995-01-03

Examiner

Atkinson, Charles E.

Patent Class

Excavating

Other Related Categories

371 225, G01R 3128

Type

Patent

Status

active

Patent number

053793030

Description

ABSTRACT:
Two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit when the system logic is being tested, that maximizes improvement to fault coverage of the system logic, are disclosed. The present invention has particular application to digital system testing. The fault coverage of the system logic is improved due to its controllability and observability are indirectly enhanced by the enhanced controllability of the embedded memory arrays. The first related method and apparatus determines the binary constant based on a testability measure selected for the system logic. The second related method and apparatus determines the binary constant based on results from automated test patterns generation for the integrated circuit. Both methods and apparatus provide a constant that is more effective than a randomly assigned binary constant, but without the expensive computations required for a binary constant determined from all possible enumeration.

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W. O. Budde "Modular Test Processor for VLSI chips and High-density PC Boards" pp. 1118-1124 1988 IEEE.
H. C. Ritter et al. `Modular BFST concept for Microprocessors` 1990 IEEE pp. 234-237.

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