Excavating
Patent
1993-11-12
1995-01-03
Harrell, Robert B.
Excavating
364DIG1, 364DIG2, 364264, 3642641, 3642643, 364265, 3642656, 364267, 3642672, 3642676, 36426791, G06F 1100, G06F 1128
Patent
active
053793013
ABSTRACT:
A microprocessor, comprising a register 18 for setting either a first mode in which a trap instruction is not executed, or a second mode in which the trap instruction can be executed is set, wherein an instruction decoding circuit 23, in case of operating in the first mode, outputs an internal signal SG1 directing execution of a subroutine call, when decoding a subroutine call instruction, to an instruction executing unit 14, and in case of operating in the second mode, outputs the internal signal SG1 directing execution of a trap when decoding the subroutine call instruction, to the instruction executing unit 14. By such a configuration, a break can be effected in a unit of subroutine under a simple control when debugging the program, and by enabling the breaking without decoding a program to be debugged, the debugging can be effected efficiently under a real time environment.
REFERENCES:
patent: 4571677 (1986-02-01), Hirayama et al.
patent: 4635193 (1987-01-01), Moyer et al.
patent: 5067073 (1991-11-01), Andrews
patent: 5121489 (1992-06-01), Andrews
Hirano Koji
Saitoh Kazunori
Sato Koichi
Harrell Robert B.
Mitsubishi Denki & Kabushiki Kaisha
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