Solid-state imaging device having no transfer error of the signa

Details Solid-state imaging device having no transfer error of the signa Solid-state imaging device having no transfer error of the signa

1997-10-30

2000-09-05

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

257231, 257233, 257241, H01L 27148, H01L 29768

Patent

active

061147176

ABSTRACT:
A solid-state imaging device that prevents the transfer errors of the signal charges from vertical charge-transfer sections to a horizontal charge-transfer section. A first plurality of buried channel regions in vertical charge-transfer sections are connected to a second buried channel region in a horizontal charge-transfer section so that the interfaces between the first plurality of buried channel regions and the second buried channel region are located to be aligned with the corresponding ends of the first plurality of gate electrodes. Thus, no potential dip nor potential barrier are generated in the vicinity of the interfaces between the first plurality of buried channel regions and the second buried channel region.

REFERENCES:
patent: 4987466 (1991-01-01), Shibata et al.
patent: 5196719 (1993-03-01), Miwada
patent: 5220185 (1993-06-01), Wada
patent: 5323034 (1994-06-01), Furumiya
patent: 5589698 (1996-12-01), Nakashiba
patent: 5770870 (1998-06-01), Nakashiba
Furumiya, M. et al., "FA 11.5: A 30Frame/s 2/3 Inch 1.3M Pixel Progressive Scan IT-CCD Image Sensor", 1997 IEEE International Solid-State Circuits Conference, ISSCC97/Session 11/Imaging Circuits and Systems/Paper FA 11.5.
Yamaguchi, T. et al., "A 1/3-inch 330k Square-Pixel Progressive-Scan IT-CCD", 1995 IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, Apr. 20-22, 1995, IEEE Electron Devices Society.

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