Slide network for an array processor

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39520068, 39580011, G06F 1580

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057650152

ABSTRACT:
In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to "slide" through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.

REFERENCES:
patent: 3537074 (1970-10-01), Stokes et al.
patent: 3544973 (1970-12-01), Borck et al.
patent: 3970993 (1976-07-01), Finnila
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4107773 (1978-08-01), Gilbreath et al.
patent: 4270170 (1981-05-01), Reddaway
patent: 4314349 (1982-02-01), Batcher
patent: 4338675 (1982-07-01), Palmer et al.
patent: 4380046 (1983-04-01), Fung
patent: 4394726 (1983-07-01), Kohl
patent: 4412303 (1983-10-01), Barnes et al.
patent: 4435758 (1984-03-01), Lorie et al.
patent: 4467422 (1984-08-01), Hunt
patent: 4468727 (1984-08-01), Carrison
patent: 4498133 (1985-02-01), Bolton et al.
patent: 4523273 (1985-06-01), Adams, III et al.
patent: 4598400 (1986-07-01), Hillis
patent: 4604695 (1986-08-01), Widen et al.
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4622650 (1986-11-01), Kulisch
patent: 4706191 (1987-11-01), Hamstra et al.
patent: 4720780 (1988-01-01), Dolecek
patent: 4736291 (1988-04-01), Jennings et al.
patent: 4739474 (1988-04-01), Holsztynski
patent: 4739476 (1988-04-01), Fiduccia
patent: 4748585 (1988-05-01), Chiarulli
patent: 4763321 (1988-08-01), Calvignac et al.
patent: 4780873 (1988-10-01), Mattheyses
patent: 4783738 (1988-11-01), Li et al.
patent: 4783782 (1988-11-01), Morton
patent: 4805091 (1989-02-01), Thiel et al.
patent: 4809159 (1989-02-01), Sowa
patent: 4809169 (1989-02-01), Sfarti et al.
patent: 4809347 (1989-02-01), Nash et al.
patent: 4814980 (1989-03-01), Peterson et al.
patent: 4825359 (1989-04-01), Ohkami et al.
patent: 4831519 (1989-05-01), Morton
patent: 4835729 (1989-05-01), Morton
patent: 4841476 (1989-06-01), Mitchell et al.
patent: 4847755 (1989-07-01), Morrison et al.
patent: 4849882 (1989-07-01), Aoyama et al.
patent: 4852048 (1989-07-01), Morton
patent: 4855903 (1989-08-01), Carleton et al.
patent: 4858110 (1989-08-01), Miyata
patent: 4860201 (1989-08-01), Stolfo et al.
patent: 4872133 (1989-10-01), Leeland
patent: 4873626 (1989-10-01), Gifford
patent: 4891787 (1990-01-01), Gifford
patent: 4896265 (1990-01-01), Fiduccia et al.
patent: 4901224 (1990-02-01), Ewert
patent: 4903260 (1990-02-01), Boettle et al.
patent: 4905143 (1990-02-01), Takahashi et al.
patent: 4907148 (1990-03-01), Morton
patent: 4910665 (1990-03-01), Mattheyses et al.
patent: 4916652 (1990-04-01), Schwarz
patent: 4916657 (1990-04-01), Morton
patent: 4920484 (1990-04-01), Ranade
patent: 4922408 (1990-05-01), Davis et al.
patent: 4925311 (1990-05-01), Neches et al.
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 4933895 (1990-06-01), Grinberg et al.
patent: 4942516 (1990-07-01), Hyatt
patent: 4942517 (1990-07-01), Cok
patent: 4942912 (1990-07-01), Aoyma et al.
patent: 4956772 (1990-09-01), Neches
patent: 4958273 (1990-09-01), Anderson et al.
patent: 4964032 (1990-10-01), Smith
patent: 4967340 (1990-10-01), Dawes
patent: 4975834 (1990-12-01), Xu et al.
patent: 4985832 (1991-01-01), Grondalski
patent: 4992926 (1991-02-01), Janke et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5005120 (1991-04-01), Ruetz
patent: 5006978 (1991-04-01), Neches
patent: 5008815 (1991-04-01), Hillis
patent: 5008882 (1991-04-01), Peterson et al.
patent: 5010477 (1991-04-01), Omoda et al.
patent: 5016163 (1991-05-01), Jesshope et al.
patent: 5020059 (1991-05-01), Gorin et al.
patent: 5021945 (1991-06-01), Morrison et al.
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5038386 (1991-08-01), Li
patent: 5041189 (1991-08-01), Tamitani
patent: 5041971 (1991-08-01), Carvey et al.
patent: 5045995 (1991-09-01), Levinthal et al.
patent: 5047917 (1991-09-01), Athas et al.
patent: 5049982 (1991-09-01), Lee et al.
patent: 5056000 (1991-10-01), Chang
patent: 5072217 (1991-12-01), Georgiou et al.
patent: 5113523 (1992-05-01), Colley et al.
patent: 5121498 (1992-06-01), Gilbert et al.
patent: 5136582 (1992-08-01), Firoozmand
patent: 5142540 (1992-08-01), Glasser
patent: 5146608 (1992-09-01), Hillis
patent: 5165023 (1992-11-01), Gifford
patent: 5170482 (1992-12-01), Shu et al.
patent: 5170484 (1992-12-01), Gorodalski
patent: 5173947 (1992-12-01), Chande et al.
patent: 5175862 (1992-12-01), Phelps et al.
patent: 5175865 (1992-12-01), Hillis
patent: 5181017 (1993-01-01), Frey, Jr. et al.
patent: 5187801 (1993-02-01), Zenios et al.
patent: 5189665 (1993-02-01), Niehaus et al.
patent: 5197130 (1993-03-01), Chen et al.
patent: 5212773 (1993-05-01), Hillis
patent: 5212777 (1993-05-01), Gove et al.
patent: 5218676 (1993-06-01), Ben-Ayed et al.
patent: 5218709 (1993-06-01), Fijany et al.
patent: 5230079 (1993-07-01), Grondalski
patent: 5239629 (1993-08-01), Miller et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5251097 (1993-10-01), Simmons et al.
patent: 5253359 (1993-10-01), Spix et al.
patent: 5265124 (1993-11-01), Staab et al.
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5297260 (1994-03-01), Kametani
patent: 5355508 (1994-10-01), Kan
patent: 5367636 (1994-11-01), Colley et al.
Sunwoo et al., "A Sliding . . . Array Processor", IEEE, 1988 pp. 537-540.
Siegel et al., "Using the Multistage . . . In Parallel Supercomputers," IEEE, 1989, pp. 1932-1953.
T.A. Kriz and M.J. Marple, "Multi-Port Bus Structure With Fast Shared Memory", IBM Technical Disclosure Bulletin, vol. 27, No. 10A, pp. 5579-5580, Mar. 1985.
H.P. Bakoglu, "Second-Level Shared Cache Implementation for Multiprocessor Computers with a Common Interface for the Second-Level Shared Cache and the Second-Level Private Cache", IBM Technical Disclosure Bulletin, vol. 33, No. 11, pp. 362-365, Apr. 1991.
Mansingh et al., "System Level Air Flow Analysis for a Computer System Processing Unit", Hewlett-Packard Journal, vol. 41 No. 5, Oct. 1990, pp. 82-87.
Tewksbury et al., "Communication Network Issues and High-Density Interconnects in Large-Scale Distributed Computing Systems", IEEE Journal on Selected Areas in Communication, vol. 6 No. 3, Apr. 1988, pp. 587-607.
Boubekeur et al., "Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors", Computer, vol. 2, Issue 4, Apr. 1992, pp. 29-39.
Korpiharju et al., "TUTCA Configurable Logic Cell Array Architecture" IEEE, Sep. 1991, pp. 3-3.1-3-3.4.
C.K. Baru and S.Y.W. Su, "The Architecture of SM3: A Dynamically Partionable Multicomputer System", IEEE Transactions on Computers, vol. C-35, No. 9, pp. 790-802, Sep. 1986.
S.P. Booth et al., "Evaluation of the Meiko Computing Surface for HEP Fortran Farming*", Computer Physics Communications 57, pp. 486-491, 1989.
S.P. Booth et al., "Large Scale Applications of Transputers in HEP: The Edinburgh Concurrent Supercomputer Project", Computer Physics Communications 57, pp. 101-107, 1989.
P. Christy, "Software to Support Massively Parallel Computing on the MasPar MP-1", 1990 IEEE, pp. 29-33.
S.R. Colley, "Parallel Solutions to Parallel Problems", Research & Development, pp. 42-45, Nov. 21, 1989.
J.R. Nickolls, "The Design of the MasPar MP-1: A Cost Effective Massivley Parallel Computer", 1990 IEEE, pp. 25-28.
J.F. Prins and J.A. Smith, "Parallel Sorting of Large Arrays on the Maspar MP-1*, The 3rd Symposium on the Frontiers of Massively Parallel Compulation", pp. 59-64, Oct., 1990.
J.B. Rosenberg and J.D. Becher, "Mapping Massive SIMD Parallelism onto Vector Architecture for Stimulation", Software-Practice and Experience, vol. 19(8), pp. 739-756, Aug. 1989.
J.C. Tilton, "Porting an Interative Parallel Region Growing Algorithm from the MPP to the Mas

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