Patent
1995-11-20
1998-06-09
Eng, David Y.
G06F 940
Patent
active
057649707
ABSTRACT:
A method and apparatus for supporting speculative execution of count and link register modifying instructions in a microprocessor is provided. The apparatus includes a queue of rename buffers storing count/link register operand data resulting from speculatively executed instructions that modify a count/link register. The queue contains a set of control buffers, wherein each control buffer contains control bits associated with a rename buffer, the control bits including an instruction identifier tag identifying a speculatively executed instruction, the operand data of the speculatively executed instruction being stored in the associated rename buffer, and an available bit indicating when the operand data no longer needs to be stored in the associated rename buffer. The apparatus control logic sets the control bits for each control buffer, including setting the instruction identifier tag to the value indicated by a dispatch unit, and selectively sets or resets the available bit based on resolution of the speculatively executed instruction.
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English language summary of Japanese Patent No. 1-180638 submitted herewith .
Rana Deepak
Schroter David A.
Dillon Andrew J.
Eng David Y.
England Anthony V. S.
International Business Machines - Corporation
Russell Brian F.
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