Semiconductor integrated circuit device with plural gates and pl

Details Semiconductor integrated circuit device with plural gates and pl Semiconductor integrated circuit device with plural gates and pl

1992-01-21

1995-01-03

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257303, 257350, 257379, 365148, 365149, H01L 2978, G11C 1124

Patent

active

053789199

ABSTRACT:
In a sea-of-gate structure gate array in which a plurality of logic gates are arrayed on a semiconductor chip, resistance devices or capacitive devices are formed without reducing the gate scale to form analog components to render the gate array into a hybrid gate array including the analog components. A number of MOS transistors to be formed without vacancies on the chip surface are formed in a thin silicon section on an insulating layer 15. The logic gates arrayed on the chip is of the SOI structure. Below the insulating layer 15, a lower capacitor electrode 12, a dielectric film 13, an upper capacitor electrode 14 and a resistance element are formed so as to be buried in an insulating film 11 on a supporting substrate 10 or in an insulating substrate. The capacitor and the resistance are led to the chip surface by means of a contact hole 23 provided in the insulating layer 15. A grinding stop 16 is formed in the insulating layer 15. The thin silicon section of the SOI structure is produced by grinding the substrate.

REFERENCES:
patent: 3407479 (1968-10-01), Fordemwalt et al.
patent: 4791610 (1988-12-01), Takemae
patent: 4803178 (1989-02-01), McCaughan
patent: 4866291 (1989-09-01), Shimada et al.
patent: 4893158 (1990-01-01), Mihara et al.
patent: 5101251 (1992-03-01), Wakamiya et al.
IBM Technical Disclosure Bulletin, vol. 35, #2, Jul. 1992, pp. 37-38, "Method to Form Very Thin So.sub.2 Films".
IBM Technical Disclosure Bulletin, vol. 35, #2, Jul. 1992, pp. 247-249, "Process for Fabrication of Very Thin Epitaxial Silicon Films Over Insulating Layers".

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