Method of logic gate reduction in a logic gate array

Details Method of logic gate reduction in a logic gate array Method of logic gate reduction in a logic gate array

1990-06-06

1993-02-23

Trans, Vincent N.

Boots, shoes, and leggings

364489, 364488, G06F 1560

Patent

active

051896290

ABSTRACT:
A method of gate reduction in a gate width limited logic array. Common sub-groups of inputs associated with an array output are collected. Logical functions are then reimplemented, using the common subgroups implemented as single gates resulting in an implementation of the logical functions that uses few active devices. The method uses a constraint typically placed on gate array logic that gates wider than four inputs cannot be used. The method is applicable to combinatorial digital logic devices only. The method of the present invention is applicable to large scale integration (LSI) and very large scale integration (VLSI) integrated circuit devices.

REFERENCES:
patent: 3778815 (1973-12-01), Wright
patent: 4600995 (1986-07-01), Kinoshita
patent: 4792909 (1988-12-01), Serlet
patent: 4823278 (1989-04-01), Kikuchi et al.
patent: 4960724 (1990-10-01), Watanabe et al.

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