Electrically programmable non-volatile semiconductor memory devi

Details Electrically programmable non-volatile semiconductor memory devi Electrically programmable non-volatile semiconductor memory devi

1992-12-31

1995-01-03

Fourson, George

Fishing, trapping, and vermin destroying

437 49, H01L 21265

Patent

active

053786432

ABSTRACT:
An A-1 transistor type flash EEPROM is disclosed. The memory cell in the EEPROM comprises: a first control gate which is formed, through a first insulating film, on a first channel region formed between a source region and a drain region. A floating gate is formed on the second channel region through a second insulating film and on the first control gate through the first interlayer insulating film. A second control gate is formed on a surface of the floating gate through a second interlayer insulating film. One end of the second control gate and one end of the first control gate are electrically connected to each other through a third control gate, thereby enhancing capacitance between the control gates and the floating gate.

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Inoue et al, "A New Stacked Capacitor Cell with Thin Box Structured Storage Node", Extended Abstract of the 21st Conference on Solid State Devices and Materials (1989), pp. 141-144.

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