Method and apparatus for generating an optimal test pattern for

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371 2233, 364717, G01R 3128

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057646570

ABSTRACT:
A method for generating an optimal serial test pattern for sequence detection. The serial test pattern comprises a first plurality of bits and is generated by a pattern generator. The method comprises generating a second plurality of bits having a first value and a least significant bit. The second plurality of bits includes less bits than the first plurality of bits. The first value of the second plurality of bits is then compared with at least one number. A next bit is then generated in the serial pattern. If the first value of the second plurality of bits is equal to the at least one number, the next bit has a same state as the least significant bit in the second plurality of bits. If the second plurality of bits is not equal to the at least one number, the next bit has a complement state of the least significant bit in the second plurality of bits. For one embodiment, the second plurality of bits comprises n bits, and the at least one number comprises one through 2.sup.n-1 inclusive. For another embodiment, the at least one number comprises 2.sup.n-1 -1 through 2.sup.n -2 inclusive.

REFERENCES:
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patent: 5390192 (1995-02-01), Fujieda
patent: 5541942 (1996-07-01), Strouss
patent: 5568437 (1996-10-01), Jamal
Mississippi State University, EE3111 Digital Devices Design Laboratory Manual, Fourth Edition, (Jan. 1994).

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