Method of erasing a high density contactless flash EPROM array

Static information storage and retrieval – Floating gate – Particular biasing

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36518516, 36518519, 36518526, 36518527, 36518529, G11C 1604

Patent

active

056151527

ABSTRACT:
The present invention provides a contactless flash EPROM array formed in a P-well in a diffused silicon substrate of N-type conductivity. To facilitate a channel erase operation, thin tunnel oxide is formed between the P-well and the overlying polysilicon floating gate EPROM cells. The array is programmed in a conventional EPROM cell array manner. However, in accordance with the invention, the channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row and holding the substrate at the supply voltage.

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Toshikatsu Jinbo et al., "A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode", IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, New York, US, pp. 1547-1553.

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