Semiconductor memory device having main word lines and sub word

Details Semiconductor memory device having main word lines and sub word Semiconductor memory device having main word lines and sub word

1996-06-07

1998-06-09

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 51, G11C 800

Patent

active

057645850

ABSTRACT:
In a DRAM device including a plurality of main row decoders and a plurality of sub row decoders, each of the main row decoders is connected to only one main word line. Each of the sub row decoders is connected to one main word line and a plurality of sub word lines. One or more of the sub word lines are activated in accordance with the activated main word line and the sub row decoders.

REFERENCES:
patent: 5416748 (1995-05-01), Fujita
patent: 5463577 (1995-10-01), Oowaki
patent: 5506816 (1996-04-01), Hirose
patent: 5519665 (1996-05-01), Chishiki
patent: 5581508 (1996-12-01), Sasaki

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