Method and apparatus for performing floating point addition

Details Method and apparatus for performing floating point addition Method and apparatus for performing floating point addition

1996-07-12

1998-06-09

Elmore, Reba I.

Boots, shoes, and leggings

36474813, G06F 738

Patent

active

057645566

ABSTRACT:
A numeric processor system is provided with a floating point adder subsystem having a set of parallel dedicated numeric processors, each of the numeric processors comprising a plurality of calculation units operative in parallel on common operands to present candidate results, at least one of each of the dedicated numeric processors producing a correct result, the dedicated numeric processors reporting status information to a control unit, wherein the control unit determines which of the candidate results is the correct result for further processing. The numeric processor system according to the invention is capable of producing a final result on a floating point computation with very low latency, that is, with very few gate delays for a complete and independent computation. The numeric processor system according to the invention is particularly useful in a computation environment where successive floating point calculations are dependent. The invention is based on decomposing a normally serial algorithm into an extensive set of parallel candidate operations on different fragments of the operands, the operations being based on time-shortening assumptions, and then choosing the correct result after the operations rather than affecting the operands and modifying the calculation in series along a critical path as status information first becomes available.

REFERENCES:
patent: 4639887 (1987-01-01), Farmwald
patent: 4999803 (1991-03-01), Turrini et al.
patent: 5063530 (1991-11-01), Ishikawa et al.
patent: 5136536 (1992-08-01), Ng
patent: 5197023 (1993-03-01), Nakayama
patent: 5247471 (1993-09-01), Hilker et al.

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