Apparatus and methods for generating cell layouts

Details Apparatus and methods for generating cell layouts Apparatus and methods for generating cell layouts

1995-08-01

1998-06-09

Voeltz, Emanuel Todd

Boots, shoes, and leggings

257204, 257206, 364488, 364489, 364490, G06F 1500

Patent

active

057645337

ABSTRACT:
An apparatus for generating a cell layout representative of a CMOS logic cell. The apparatus includes a pMOS transistor layout generator for generating a first set of layout data representative of a plurality of substantially similar pMOS relatively low strength transistor groups that are oriented along a first direction. The apparatus further includes an nMOS transistor layout generator for generating a second set of layout data representative of a plurality of substantially similar nMOS relatively low strength transistor groups that are also oriented along the first direction. The apparatus further includes a polysilicon conductor generator for generating a third set of layout data representative of a plurality of polysilicon conductors, which are used for coupling transistors in the plurality of substantially similar pMOS relatively low strength transistor groups with complementary ones of transistors in the plurality of substantially similar nMOS relatively low strength transistor groups, to create a plurality of low strength gates. There is further included a metal one conductor generator for generating a fourth set of layout data representative of a first metal one conductor. The first metal one conductor is coupled to the plurality of polysilicon conductors to create a higher strength gate out of the plurality of low strength gates.

REFERENCES:
patent: 4928160 (1990-05-01), Crafts
patent: 5313079 (1994-05-01), Brasen et al.
patent: 5343058 (1994-08-01), Shiffer, II
patent: 5348902 (1994-09-01), Shimada et al.
patent: 5420447 (1995-05-01), Waggoner
Xia et al. "Optimization-Based Placement Algorithm for BIOMOS Leaf Cell Generation," IEEE, 1994, pp. 1227-1237.

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