Dynamic propagation delay calculation using an array of storage

Details Dynamic propagation delay calculation using an array of storage Dynamic propagation delay calculation using an array of storage

1996-04-08

1998-06-09

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364489, 364490, 395500, G06F 1750

Patent

active

057645264

ABSTRACT:
Described herein is a computer-implemented method of dynamically determining propagation delays through a system of directedly interconnected components. An array of storage cells is maintained in a computer. The storage cells are logically referenced by row and column numbers. As components are added to the system, they are assigned enumerated component numbers. A particular storage cell corresponds to a potential network of directed paths between upstream and downstream components having component numbers equal to the row and column numbers of the particular storage cell, respectively. When the array is maintained in accordance with the invention, a cell contains the propagation delay from the corresponding upstream component to the corresponding downstream component if there is a path from the upstream component to the downstream component. Upon specifying a new component in the system, the array is increased in size by one row and one column. The invention includes writing the individual propagation delay of the new component to the storage cell having row and column numbers equal to the component number of the new component. Upon specifying a new connection from a component q to a component p, all storage cells are identified that correspond to a directed path network including a non-looping directed path completed by the new connection. The cells so identified are those that are both (a) in a column having a propagation delay entry in row p, and (b) in a row having a propagation delay entry in column q. Identified storage cells are updated with the propagation delay of the newly completed path, but only if the new value is greater than the prior entry and the path does not contain a loop.

REFERENCES:
patent: 5535145 (1996-07-01), Hathaway
patent: 5572717 (1996-11-01), Pederson
patent: 5596505 (1997-01-01), Steinweg et al.
patent: 5621895 (1997-04-01), Weis et al.

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