Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Patent
1995-09-28
1997-03-25
Mis, David
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
331 1A, 331 11, 331 17, 331 20, 327157, 327159, 348540, 360 51, 375376, H03L 7087
Patent
active
056148704
DESCRIPTION:
BRIEF SUMMARY
The invention relates to an arrangement for generating a clock signal.
Digital video signal processing systems with features such as on-screen display of text and picture-in-picture for both television receiver and video tape recorder signal sources may require a clock signal that is phase locked to a horizontal synchronization signal, referred to as line-locked clock. It may be advantageous to form a phase-locked loop (PLL) system for line-locked clock generation for use as a building block in large scale CMOS video signal processing integrated circuits. In such PLL, it may be desirable to have, for example, a clock frequency that ranges from 25 MHz to 40 MHz with a jitter that is less than 2 nS. For such PLL it may be desirable to utilize only one pin for off-chip components. It may also be desirable to use the PLL system with each of the NTSC, PAL and SECAM systems.
It may also be desirable to operate the PLL with an input sync signal encountered in low-cost consumer video tape recorders without time-base correction, where the horizontal sync can periodically make large phase changes such that the clock signal tracks such sync signal. It may be further desirable to rapidly reduce phase and frequency errors and minimize overshoot and jitter as the PLL settles into phase lock. In addition, it may be desirable to have the PLL discriminate between true output clock phase/frequency errors and those arising from contamination of the input horizontal sync signal with noise bursts or occasional missing pulses.
A PLL system, embodying an inventive feature, utilizes both digital and analog control of an R-C Voltage-Controlled Oscillator to acquire and maintain phase lock of an output clock with respect to an input horizontal sync signal. Depending on the magnitude and consistency of the output clock phase and frequency error, the system automatically selects one of, for example, five control modes of operation of varying sensitivity. The control modes of operation are such that large errors result in large, coarse corrective actions, and small errors result in small, or fine corrective actions.
In a PLL, embodying a different inventive feature, a frequency error of an oscillator output signal is measured with respect to a frequency of a synchronizing signal. When the frequency error is greater than a predetermined threshold value in a given period of the oscillator output signal the period is counted. When the number of consecutive periods in which the frequency error exceeds the threshold level becomes greater than, e.g., 32, the PLL begins operating in a coarse frequency correction mode. As long as the number of consecutive counted periods do not exceed 32, the PLL operates in an idle mode of operation. In the coarse frequency correction mode, switched capacitors that control the oscillator frequency are sequentially coupled or decoupled in steps in a manner to reduce the frequency error. In the idle mode of operation, the frequency of the oscillator does not change.
Advantageously, by counting 32 periods, the frequency of the oscillator does not change during a vertical blanking interval, when the equalizing pulses produce a frequency error that is greater than the threshold value. The frequency of the oscillator does not change, during vertical blanking, because the number of equalizing pulses is too small to produce 32 consecutively counted periods in which the frequency error exceeds the threshold level. It follows that the equalizing pulses do not cause a disturbance in the oscillator frequency.
An apparatus, embodying an inventive feature, for generating an oscillatory signal that is locked to a synchronizing signal includes a source of the synchronizing signal at a frequency that is related to a horizontal scanning frequency. The frequency of the synchrionizing signal has a value that is different during a vertical trace interval from that during a vertical blanking interval of a vertical scanning cycle. A controllable oscillator generates the oscillatory signal. A frequency error is measured between the
REFERENCES:
patent: 4484152 (1984-11-01), Lee
patent: 4514705 (1985-04-01), Harzer
patent: 4516118 (1985-05-01), Wahlquist
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 4594564 (1986-06-01), Yarborough, Jr.
patent: 4616259 (1986-10-01), Moran et al.
patent: 4654604 (1987-03-01), Smith et al.
patent: 4745372 (1988-05-01), Miwa
patent: 4797634 (1989-01-01), Filliman
patent: 4812783 (1989-03-01), Honjo et al.
patent: 4827225 (1989-05-01), Lee
patent: 4837781 (1989-06-01), Hickling
patent: 4843332 (1989-06-01), Cok et al.
patent: 4876518 (1989-10-01), Perkins
patent: 4878231 (1989-10-01), Cok
patent: 4881048 (1989-11-01), Auneau et al.
patent: 4890071 (1989-12-01), Curtis
patent: 4918405 (1990-04-01), Herleikson
patent: 4920320 (1990-04-01), Matthews
patent: 4920322 (1990-04-01), Ruijs
patent: 4929918 (1990-05-01), Chung et al.
patent: 4935706 (1990-06-01), Schenberg
patent: 4974081 (1990-11-01), Yokogawa
patent: 5159292 (1992-10-01), Canfield et al.
patent: 5162910 (1992-11-01), Willis
patent: 5172076 (1992-12-01), Brown
patent: 5239274 (1993-08-01), Chi
patent: 5298870 (1994-03-01), Cytera et al.
patent: 5363419 (1994-11-01), Ho
patent: 5382922 (1995-01-01), Gersbach et al.
PCT/US94/04291, filed 19 Apr. 1994, Sauer et al., A Phase Lock Loop With Error Consistency Detector (RCA 87144).
PCT/US94/04307, filed 19 Apr. 1994, Sauer et al., A Phase Logic Loop With Error Measurement and Correction In Alternate Periods (RCA 87598).
PCT/US94/04404, filed 19 Apr. 1994, Sauer et al., An Oscillator With Switched Reactive Elements (RCA 87599).
Campbell, III Edward R.
Rodda William E.
Sauer Donald J.
Henig Sammy S.
Laks Joseph J.
Mis David
RCA Thomson Licensing Corporation
Tripoli Joseph S.
LandOfFree
Phase lock loop with idle mode of operation during vertical blan does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase lock loop with idle mode of operation during vertical blan, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase lock loop with idle mode of operation during vertical blan will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2206816