Fishing – trapping – and vermin destroying
Patent
1996-01-29
1997-03-25
Dang, Trung
Fishing, trapping, and vermin destroying
437 69, 437978, H01L 2176
Patent
active
056144342
ABSTRACT:
A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a sacrificial layer is deposited on a laminate comprising a substrate having thereon stacked layers. A photo-resist mask which defines the active regions is then formed on the top of the sacrificial layer and an anisotropic etching is used to remove the unmasked sacrificial layer and the stacked layers. A portion of the photo-resist is eroded, and the exposed sacrificial layer is removed. After the photo-resist is removed, channel-stop ions are implanted, and the portion of the stacked layers not covered by the sacrificial layer are etched. After the sacrificial layer is completely removed, isolation regions are formed on the exposed substrate. The channel-stop region is self-aligned to the resulting field oxide and the isolation structure is free of impurity encroachment effect.
REFERENCES:
patent: 4829019 (1989-05-01), Mitchell et al.
patent: 5104829 (1992-04-01), Shida
patent: 5208181 (1993-05-01), Chi
patent: 5286672 (1994-02-01), Hodges et al.
Dang Trung
United Microelectronics Corp.
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