Method for fabricating EEPROM with control gate in touch with se

Details Method for fabricating EEPROM with control gate in touch with se Method for fabricating EEPROM with control gate in touch with se

1995-07-17

1997-03-25

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437 49, H01L 218247

Patent

active

056144296

ABSTRACT:
An EEPROM comprising a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.

REFERENCES:
patent: 4988635 (1991-01-01), Ajika et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5498559 (1996-03-01), Chang

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