Parallel multiplier with a modified booth algorithm

Details Parallel multiplier with a modified booth algorithm Parallel multiplier with a modified booth algorithm

1986-07-22

1988-12-13

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

047916010

ABSTRACT:
A parallel multiplicator including adder circuits based on Booth's algorithm is disclosed. All of the adders of a plurality of rows are constructed based on the carry save system. When the negative partial-product signal is input, the "2's complement" generating signals CB0 to CB3 for the LSB of the negative partial-product signal are input to the bit adder in the lowest order row which corresponds to the LSB of the negative partial-product signal.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4484301 (1984-11-01), Borgerding et al.
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4646257 (1987-02-01), Essig et al.

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