Boots – shoes – and leggings
Patent
1994-12-22
1996-08-06
Swann, Tod R.
Boots, shoes, and leggings
395456, 395459, 364DIG1, G06F 1208
Patent
active
055443400
ABSTRACT:
A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.
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Doi Toshio
Hayashi Takehisa
Ishibashi Kenichi
Takemoto Takeshi
Hitachi , Ltd.
Peikari James
Swann Tod R.
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